1. Field of the Invention
The present invention relates to a circuit and method for testing an analog-digital converter (ADC).
2. Description of the Related Art
FIG. 9 is a block diagram for explaining a method for testing an ADC 11 in a conventional large scale integrated (LSI) circuit 500 which includes the ADC 11 and an internal logic circuit 12 operating according to an output from the ADC 11. When the LSI circuit 500 tests the performance of the ADC 11, an analog input signal AIN is inputted through an input terminal to the ADC 11, and output terminals (i.e., MONITOR terminals), to which a 16-bit output signal from the ADC 11 is inputted, are monitored to judge the performance of the ADC 11.
FIG. 10 is a block diagram for explaining another method for testing an ADC 11 in another conventional LSI circuit 600 which includes the ADC 11 and an internal logic circuit 12 operating according to an output from the ADC 11. When the LSI circuit 600 tests the performance of the ADC 11, an external digital-analog converter (DAC) is connected to output terminals of the ADC 11, an analog input signal AIN is inputted through an input terminal to the ADC 11, and an output terminal (i.e., MONITOR terminal) of the DAC 21 is monitored to judge the performance of the ADC 11. See Japanese Patent Application Kokai (Laid-Open) Publication No. 11-326465 (Patent Document 1), for example.
However, in the conventional testing method by the LSI circuit 500 shown in FIG. 9, it is difficult to judge the performance of the ADC 11 in consideration of a conversion error of the ADC 11, in particular, a conversion error around zero-crossing or digit-carrying. More specifically, when pass/fail decision is made on 8-bit data in 2 s complement form with 1-LSB (least significant bit) error permitted, only first 7 bits are cared in the decision.
When an expected value of an output from the ADC 11 is “00000000” and a tolerable error is 1-LSB, not only a converted value “00000000” but also converted values “00000001” and “11111111” should be determined as pass results. Although setting an LSB as a “Don't Care” bit (which means that any bit value is permitted) allows the converted value “00000001” to be determined as pass result, there is a problem that the converted value “11111111” is difficult to be determined as pass result.
In the conventional testing method by the LSI circuit 600 shown in FIG. 10, an analog output signal produced by the DAC 21 is monitored. However, it is a problem that measurement result varies according to accuracy of the DAC 21 and an accurate decision of the performance of the ADC 11 cannot be obtained. There is another problem that time for testing increases because the DA conversion in the DAC 21 takes much time.